| Date: | 01.10.2026 - 24.01.2027 |
| Aim of the course: | To equip learners with systematic knowledge and skills for the development of artificial intelligence chips. |
| Target group: | Company experts, engineers and chip designers who develop or select chips for running AI applications. |
| Prerequisites: | Bachelor's degree. Prior knowledge of machine learning and digital electronics design. |
| Topics: | IAS0650 Chips for AI IAS0640 HDL in Digital Systems Design |
| Study results: | 1. Compares CNNs, RNNs, and Transformers and understands their impact at the operator level. 2. Distinguishes between Edge and Cloud AI trade-offs, including latency, privacy, cost, energy consumption, and availability. 3. Applies quantization and pruning techniques to reduce latency, memory usage, and energy consumption while maintaining accuracy. 4. Compares CPUs, GPUs, TPUs, and ASIC accelerators for AI workloads. 5. Explains the trade-offs between FPGA- and ASIC-based solutions for AI acceleration and demonstrates proficiency in FPGA design methodology. 6. Understands the hardware architecture of AI System-on-Chip (SoC) solutions, can use the SystemVerilog hardware description language, and understands the key stages of chip design (synthesis and physical implementation). |
| Modules: | [koosneb moodulitest] Riistvara kirjelduskeel digitaalsüsteemide disainis Tehisintellekti kiibid |
| Learning outcomes: | Engineering, manufacturing and construction |
| Course language: | in English |
| Volume: | lectures: 128 academic hours independent studies: 184 academic hours |
| Credit points (ECTS): | 12.0 |
| Graduation document: | TalTech certificate |
| Lecturer: | Jaan Raik, Maksim Jenihhin, Mohammad Hasan Ahmadilivani, Natalia Cherezova |
| Contact: | Jaan Raik, 6202257, jaan.raik@taltech.ee |
| Price: | 1920 EUR / participant |
| Registration start: | 03.07.2026 00:00 |
| Registration deadline: | 14.09.2026 |
| Place: | Online |